system verilog - How does 'event' works? -


i'm studying systemverilog event data types. can't understanda simulation results.

how event works in systemverilog?

update

1 module events();   2 // declare new event called ack   3 event ack;    4 // declare done alias ack    5 event done = ack;    6 // event variable no synchronization object   7 event empty = null;       9 initial begin  10    #1  -> ack;  11    #1  -> empty;  12    #1  -> done;  13    #1  $finish;  14 end  15   16 @ (ack)  17 begin  18   $display("ack event emitted");  19 end  20   21 @ (done)  22 begin  23   $display("done event emitted");  24 end  25   26 /*  27 @ (empty)  28 begin  29   $display("empty event emitted");  30 end  31 */  32   33 endmodule

how show following?

 ack event emitted  done event emitted ack event emitted <== don't understand here why happens?  done event emitted

i think should this.

 ack event emitted   done event emitted   done event emitted

i think may confused why events printed multiple times? have @ line5:

event done = ack;

now ack , done synonymous each other, whenever 1 event triggered other well, since each triggered once 4 printouts.


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