system verilog - How to access the structures from testbench -

typedef struct packed signed{     bit valid;     bit tag;     bit signed[31:0] data; }my_data;  module structure_example5(input clk,input my_data a);  always@(posedge clk) begin     if(a.tag>a.valid)begin       $display("g");     end     else begin       $display("l");     end   end  endmodule:structure_example5  //test bench  module structure_example5_tb;  reg clk;   reg a.tag,a.valid;      structure_example5 uut (clk,a);    initial begin    #5     clk=0;    forever      #5clk=!clk;   end    initial begin     a.tag=1'b1;     a.valid=1'b0;     #50     $finish();   end  endmodule:structure_example5_tb 

until , unless struct of single direction there won't difficulty in connecting test-bench , dut ports together

here @ test-bench code comment out reg declaration of structure members , use structure declaration

//reg a.tag,a.valid;   my_data a; 

and try run code, corrected/working code can found in link

update:

as per dave's suggestion, recommended when sharing typedefs multiple modules using package better solution, use, define typedefs inside package , import package in required module, can module including testbench , dut.

eg:

package my_pkg;     typedef struct packed signed{           bit valid;           bit tag;           bit signed[31:0] data;       }my_data; endpackage 

and whenever require content of package inside module use

import my_pkg::*;   

also updated link mentioned above package