system verilog - What is advantage of structure? -

i'm verilog user, unfamiliar systemverilog.

now i'm trying study structure literals.

what advantage of using structure?

structure in systemverilog more or less similar structure usage in c-language, structure collection of different data types, variables or constants under single name. more details can refer systemverilog lrm ieee std 1800-2012 ♦ 7.2 structures

i here explain more common usage , advantage of structures.

the declaration of structure can done variable or nets, structure whole can declared variable using var keyword , structure can defined net using verilog data type wire or tri, when defined net type members of structure should 4-state types.

structure variable:

var struct {  logic [15:0] a, b; logic [ 7:0] data; logic [31:0] width; } data_word_var; 

structure net:

wire struct {  logic [15:0] a, b; logic [ 7:0] data; logic [31:0] width; } data_word_net; 

if don't mentioned type of structure default net type , note net type variable cannot declared inside structure despite whole structure can of net type.

structure can initialized whole

data_word_net dw = ’{16'hf0f0, 16'h1010, 8’d3, 0}; 

or individual members can initialized

data_word_net dw; dw.data = 8'b1011_1111; 

it possibe can initialize using member names

data_word_net dw = ’{a:16'hf0f0, b:16'h1010, data:8’d3, width:0}; // legal data_word_net dw = ’{a:16'hf0f0, data:8’d3, b:16'h1010, width:0}; // legal data_word_net dw = ’{a:16'hf0f0, 8’d3, 16'h1010, width:0}; // illegal(all members should mentioned not mix both) 

also members can initialized default values using default keyword

typedef struct { real r0, r1; int i0, i1; logic [ 7:0] a; logic [23:0] addr; } data_word; data_word dw; dw = ’{ real:1.0, default:0, r1:3.1415 }; 

structure can used through module ports

package my_pkg; typedef struct { logic [31:0] a, b; } input_ports;  typedef struct { logic [63:0] y; } output_ports; endpackage  module alu (input my_pkg::input_ports inp,  output my_pkg::output_ports outp,  input wire clock);  ... endmodule 

structure can used arguments tasks , functions

module dut (...); ... typedef struct {  logic [31:0] a, b; logic [63:0] width; logic [15:0] addr; } i_pins; function alu (input i_pins connect); ... endfunction endmodule 

in addition above advantages language supports array of structures in packed , unpacked format shown below

typedef struct packed { // packed structure logic [7:0] a; logic [7:0] b; } packet_t; packet_t [15:0] packet_array; // packed array of 16 structures  typedef struct { // unpacked structure int a; real b; } data_t; data_t data_array [15:0]; // unpacked array of 16 structures