verilog - Mux Implementation -

i'm trying make 2x1 mux in verilog, variation each input technically 2 inputs, , same goes output. however, still behaves 2x1 mux. code looks this:

module mux                                                       (   output [11:0] out_0,   output [11:0] out_1,   input sel,   input [11:0] in_a_i,   input [11:0] in_b_i,   input [11:0] in_a_q,                  input [11:0] in_b_q )                       assign out_0 = (sel) ? in_a_i : in_b_i;                assign out_1 = (sel) ? in_a_q : in_b_q;                           endmodule 

when try build in xilinx however, i'm given oh useful error:

syntax error near "assign"

i don't understand what's wrong assign line, missing simple?

missing semicolon (;) after module declaration.

module mux (   output [11:0] out_0,   output [11:0] out_1,   input sel,   input [11:0] in_a_i,   input [11:0] in_b_i,   input [11:0] in_a_q,                  input [11:0] in_b_q )  ;