I am confusing some assembly code about enable PE within boot/setup.s file in Linux 0.11 -



related assembly codes located in boot/setup.s , paste them below:

    mov ax,#0x0001        ! protected mode (pe) bit      lmsw ax               ! bit!     jmpi 0,8              ! jmp offset 0 of segment 8 (cs)

the first 2 lines have made corresponding bit changes in cr0 control register.
so,my problem :
    when instruction lmsw ax being executed, ip register points next instruction jmpi 0,8 .
more exactly , at point , cs:ip points memory location of instruction jmpi 0,8 .
but after execution of instruction lmsw ax, pe mechanism enabled. cs value
represents segment selector, but corresponding gdt description entry not
prepared it. the gdt contains 2 valid entries located in 1 , 2 respectively.so,
think next instruction specified cs:ip not instruction jmpi 0,8.
cs:ip points invalid memory address. above last instruction jmpi 0,8 which used place right values cs , eip registers cannot reached. know wrong because linux 0.11 verifying long term practice. please me point mistakes make.thanks much.

the cpu doesn't selectors in gdt (or ldt) every time segment register used. reads descriptor table in memory when segment register loaded. stores information in segment descriptor cache.the same thing happens in real mode, when segment register loaded value, value used create entry in descriptor cache. whenever segment used, both in real , protected mode, processor uses values stored in cache.

when switch real mode protected mode none of segment registers change , none of entries in descriptor cache change. cache entry cs register remains same before, , cpu executes following instruction expected. it's not until following far jump instruction executed value of cs register changes, replaces old real mode descriptor entry new protected mode entry.


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